The Global System for Mobile Communication (GSM) standard is used in many parts of the world (e.g. Europe and Asia) to enable digital wireless communication to be conducted between mobile units, such as mobile telephones. With GSM, it is possible for a plurality of mobile units to concurrently share the same frequency to conduct communications. Thus, with GSM, it is possible to accommodate more mobile units per frequency than with traditional analog systems.
As noted above, GSM enables digital information to be sent wirelessly. To send digital information using GSM, the digital information is first modulated onto a carrier signal. With GSM, digital information is typically modulated using Gaussian Minimum Shift Keying (GMSK), a well-known technique. GMSK signals have two components, an in-phase component and a quadrature-phase component. Both components are needed to properly modulate and demodulate a set of digital information. Each of the components is typically represented by a predetermined waveform. Further, each waveform corresponds to a particular set of digital information. Thus, for example, for the set of digital information “0110”, there is a corresponding in-phase waveform and a corresponding quadrature-phase waveform. The in-phase waveform represents an in-phase signal component having the digital information “0110” already modulated thereon, and the quadrature-phase waveform represents a quadrature-phase signal component having the digital information “0110” already modulated thereon. These waveforms are predetermined and pre-stored. Thus, when it comes time to modulate a set of digital information (e.g. 0110), all that needs to be done is to access the waveforms corresponding to that set of digital information.
Typically, each waveform corresponds to a particular set of four digital bits. With four bits, there are sixteen possible combinations of 1's and 0's. Thus, there are sixteen possible in-phase waveforms and sixteen possible quadrature-phase waveforms. Due to symmetry, however, it is possible to reduce the number of waveforms from sixteen to four, so that in practice, only four in-phase waveforms and four quadrature-phase waveforms are pre-stored.
Each waveform is typically stored in digital form. This means that each waveform is represented as an X number of points, where each point represents a sample of the waveform. In some implementations, X is set to eight, so that each waveform is represented as eight sample points. Each sample point takes the form of a set of Y bits. In some implementations, Y is set to ten; thus, each point is expressed as a ten bit value.
Because the waveforms are stored in digital form, they are converted to analog signals before being passed on to a transmitter. With reference to FIG. 1, there is shown an apparatus that can be used to carry out this conversion. The apparatus of FIG. 1 comprises two storages 102(1), 102(2), each typically taking the form of a read-only-memory (ROM), and two digital-to-analog converters (DAC's) 104(1), 104(2). Storage 102(1) stores the digital representations of the in-phase waveforms, and storage 102(2) stores the digital representations of the quadrature-phase waveforms.
In operation, a set of digital information (e.g. 0110) is determined to be modulated. Accordingly, the in-phase waveform corresponding to that set of digital information is read out of storage 102(1), and the quadrature-phase waveform corresponding to that set of digital information is read out of storage 102(2). DAC 104(1) converts each point of the in-phase waveform into a corresponding analog signal. Similarly, DAC 104(2) converts each point of the quadrature-phase waveform into a corresponding analog signal. Once generated, these analog signals are passed on to a transmitter for transmission. In this manner, the set of digital information is modulated and transmitted.
The apparatus shown in FIG. 1 functions satisfactorily if: (1) the DAC's 104(1), 104(2) exhibit ideal behavior; and (2) the DAC's 104(1), 104(2) are completely symmetrical. In actual implementation, however, this is rarely, if ever, the case. In practice, the DAC's 104 usually suffer from several deviation effects. A first deviation effect is referred to herein as amplitude deviation. Amplitude deviation is manifested when, given a certain digital input, a DAC 104 outputs an analog signal having an amplitude that is different than the amplitude that the DAC 104 is supposed to output. For example, the DAC 104 may output an analog signal with an amplitude of 0.9 volts when it is supposed to output an analog signal with an amplitude of 1 volt. The effects of amplitude deviation are exacerbated if the DAC's 104 are not symmetrical, because in that case, not only is there amplitude deviation, there is also an amplitude imbalance between the two DAC's 104, such that given the same digital inputs, the two DAC's 104 output analog signals of different amplitudes. This can lead to serious errors.
Another deviation effect experienced by the DAC's 104 is a direct current (DC) offset. This DC offset causes the output analog signals of a DAC 104 to be shifted by a certain DC amount. Again, this can lead to errors. Amplitude deviation and DC offset are just some of the imperfect behaviors that can be exhibited by the DAC's 104. Others, such as non-linearity, may also be exhibited.
To remedy the DC offset and amplitude deviation effects, the apparatus shown in FIG. 2 has sometimes been used. The apparatus of FIG. 2 is basically the same as the apparatus of FIG. 1, except that it further comprises a pair of DC offset adders 206 and a pair of analog compensation circuits 208. The DC offset adders 206 are used to compensate for the DC offset effects of the DAC's 204, while the analog compensation circuits 208 are used to adjust the analog outputs of the DAC's 204 to compensate for the amplitude deviations and the amplitude imbalance between the two DAC's 204.
The apparatus of FIG. 2 is effective in some limited circumstances. However, it has a number of significant drawbacks. A first drawback is that it requires the design and implementation of analog compensation circuits 208. Compensation circuits capable of adequately and accurately compensating for the amplitude deviations and amplitude imbalance of the DAC's 204 are very difficult and costly to design. Thus, these circuits add significant complexity and cost to the apparatus. A second drawback relates to the DC offset adders 206. Notice that the adders 206 are placed between the storages 202 and the DAC's 204. This means that the adders 206 need to operate every time any waveform is read from the storages 202. To prevent degrading the performance of the apparatus, the adders 206 need to be relatively high-speed adders. Such adders are costly to implement, and consume significant power. Yet another drawback of the apparatus is that it does not address the non-linearity effects of the DAC's 204 at all. These effects can lead to further errors.
As discussed above, the mechanisms currently available for modulating signals leave much to be desired. As a result, an improved modulating mechanism is needed.